Clock divider circuits are useful in a number of applications, particularly in counters, where a complete cycle of an output signal represents a predetermined number of incoming clock cycles. The cycles of the output signal can be used to "count" the incoming clock cycles.
It is desirable for such clock divider circuits to work at low power and at high frequencies. For example, desired operating parameters might be a current consumption of 10 .mu.A at a supply voltage of 3.3 V, with an operating frequency of around 100 MHz. It is also desirable that such divider circuits consume a minimum amount of silicon when implemented on an integrated circuit.
Existing counters are generally based on binary counters. As the basic unit for a binary counter is a divide-by-two unit, extra logic is required to implement counts by odd numbers. This extra logic reduces the highest operating frequency obtainable by the counting circuit and also consumes chip area. Moreover, existing binary counters rarely produce an output signal which has a 50% duty cycle.
Signals having a 50% duty cycle are particularly desirable because in such signals, there is the maximum possible time for the rising and falling edges to achieve safe logic levels. This reduces pulse shrinkage and the consequent uncertainties, both in terms of amplitude and timing of the signal. Moreover, some circuits use both the rising and falling edges of a clock signal, so that it provides greater design flexibility to have a timing point midway through a clock cycle.
The present invention provides a dividing circuit which exhibits an improvement in operating frequency with reduced silicon consumption, particularly for dividing by an odd integer, referred to by N herein.